1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor device, and a method for manufacturing the semiconductor integrated circuit and a method for manufacturing the semiconductor device, and more particularly to an isolation used for the semiconductor integrated circuit or the semiconductor device, a sidewall spacer of a MOS transistor, wirings for connecting elements of the semiconductor integrated circuit, and layer insulation of the wirings.
2. Description of the Background Art
FIGS. 36 and 37 are typical views showing an example of a semiconductor integrated circuit having an isolation region according to the prior art. FIG. 36 shows a planar layout of the semiconductor integrated circuit. FIG. 37 shows a sectional structure taken along the line Axe2x80x94A in FIG. 36.
A MOS transistor shown in FIGS. 36 and 37 is a component of a semiconductor memory cell, for example.
In FIGS. 36 and 37, the reference numeral 1 denotes a semiconductor substrate, the reference numeral 2 denotes a shallow trench isolation (hereinafter referred to as an STI) which is provided by forming a trench having a depth of about 0.2 to 0.3 xcexcm on the semiconductor substrate 1 and burying an insulator in the trench, the reference numerals 3a to 3d denote source/drain regions formed on a principal plane of the semiconductor substrate 1, the reference numeral 4 denotes a gate oxide film stacked on the semiconductor substrate 1 or the STI 2, the reference numeral 5 denotes a polysilicon gate electrode stacked on the gate oxide film 4, the reference numeral 6 denotes a silicide film stacked on the polysilicon gate electrode 5, the reference numeral 7 denotes an oxide film stacked on the silicide film 6, the reference numeral 8 denotes a sidewall spacer formed on sidewalls of the gate oxide film 4, the polysilicon gate electrode 5, the silicide film 6 and the oxide film 7, the reference numeral 11 denotes an interlayer film formed by covering the principal plane of the semiconductor substrate 1, and the reference numeral 12 denotes a metal wiring formed on the interlayer film 11. In this specification, the STI represents a method for isolating a set of elements which are adjacent to each other. In addition, the STI also represents a structure used for the isolating method. The STI 2 is formed in a peripheral portion of an active semiconductor region including the source/drain regions 3a to 3d. A MOS transistor formed by the source/drain regions 3a to 3d, the semiconductor substrate 1, the gate oxide film 4 and the gate electrode 5 is used for a memory cell, for example.
The gate oxide film 4, the polysilicon gate electrode 5, the silicide film 6, the oxide film 7 and the sidewall spacer 8 form signal lines 9a to 9c. Examples of a material of the silicide film 6 include tungsten silicide (WSi) and titanium silicide (TiSi). In general, the oxide film 7 is made of a silicon oxide film (SiO). The silicon oxide film has a resistivity of about 2xc3x971016 xcexa9xc2x7cm.
A field transistor 10 shown in FIG. 37 comprises the STI 2, the wire 9b provided on the STI 2, and the source/drain regions 3b and 3c provided on both sides of the STI 2. The field transistor 10 is a parasitic transistor using a gate oxide film as the STI 2.
Operation of a semiconductor memory cell is affected by the following properties:
1. Isolation characteristics;
2. Wiring capacitance;
3. Gate-to-source capacity and gate-to-drain capacitance; and
4. Stress applied to a gate electrode by formation of silicide.
The operation of the semiconductor memory cell is greatly affected by a quantity of a leak current and a magnitude of an allowable voltage between elements isolated in the isolation region which are included in the isolation characteristics listed in the item 1. It is desirable that the allowable voltage between the elements isolated in the isolation region should be greater and a smaller quantity of the leak current should flow between the elements through the isolation region.
As a method for obtaining such desirable isolation characteristics, it is proposed that a threshold voltage of the field transistor 10 parasitic in the isolation region should be increased. A threshold voltage Vth of a MOS transistor formed by using a silicon substrate is calculated by Equation 1, wherein the threshold voltage is represented by Vth, a Fermi level is represented by xcfx86f, a flat band voltage is represented by VFB, a gate capacitance is represented by C0, a dielectric constant of silicon is represented by KS1, a permittivity of a vacuum is represented by xcex50, a unit charge is represented by q, an acceptor concentration is represented by NA, and a source-to-substrate voltage is represented by VBS. The dielectric constant KSi of the silicon is about 11.7.                              V          th                =                              2            ⁢                          φ              f                                +                      V            FB                    +                                    1                              C                0                                      ⁢                                                            2                  ⁢                                                            K                      Si                                        ·                                          ϵ                      0                                        ·                    q                    ·                                          N                      A                                        ·                    2                                    ⁢                                      φ                    f                                                  +                                  V                  BS                                                                                        (        1        )            
The gate capacitance C0 per unit area of the MOS transistor is calculated by Equation 2, wherein a dielectric constant of a silicon oxide film is represented by KSiO2 and a thickness of a gate oxide film is represented by t0x. The dielectric constant KSiO2 of the silicon oxide film is about 3.9.                              C          0                =                                            K                              SiO                ⁢                                  xe2x80x83                                ⁢                2                                      ·                          ϵ              0                                ⁢                      1                          t                              0                ⁢                X                                                                        (        2        )            
The gate oxide film of the field transistor 10 acts as the STI 2. Therefore, as the dielectric constant of the STI 2 is reduced, the threshold voltage of the field transistor 10 is increased. After all, a dielectric constant of an insulator forming the STI 2 should be reduced in order to increase a voltage which can be isolated by the STI 2 and to decrease the quantity of the leak current.
In general, it is required that a size of a DRAM should be reduced according to a change of generation of the DRAM. In order to reduce an opening width of the STI 2 by a scaling law, a permittivity of the STI 2 should be decreased. The reason is as follows. It is required that an opening width of a trench should be reduced and a depth of the trench should be decreased if a shape of the STI 2 is to be changed by the scaling law. However, this requirement causes the isolation characteristics to be deteriorated. If the opening width of the trench is reduced and the depth of the trench is increased, it becomes hard to fill the trench with an insulator.
For example, Japanese Patent Application Laid-Open Gazette No. 8-46028 has disclosed that a trench is filled with a material whose dielectric constant is less than 3.3, that is, a polyimide or polymeric spin-on glass (SOG) in place of silicon dioxide (SiO2). However, it is difficult to fill the trench having a small opening width with an organic substance including a dielectric material such as the SOG. Furthermore, the disclosed element structure has no height difference between a semiconductor surface and a surface of the trench. Therefore, it is hard to perform mask alignment with high precision. For example, Japanese Patent Application Laid-Open Gazette No. 4-151850 has described an example in which a vacancy exists in a PSG (silicate glass) in an isolation trench. However, the vacancy described in the publication is generated by chance on only a part of the PSG in the isolation trench and is not intended to reduce a permittivity of the isolation trench. In particular, the invention described in the publication relates to a manufacturing method for preventing the vacancy formed on a bottom of the isolation trench from rising to a surface by reflow of the PSG, wherein the isolation trench is enlarged corresponding to the vacancy. A sectional area of the PSG through which an electric field is mainly transmitted is not reduced as compared with the prior art. Thus, the publication has not disclosed a method for manufacturing a semiconductor integrated circuit which can reduce the permittivity of the isolation trench.
As a method for enhancing the isolation characteristics, Japanese Unexamined Patent Publication No. 5-160251 has disclosed an isolation trench having a void 25 on the inside as shown in FIGS. 38 and 39, for example. In order to form such an isolation trench, a passivation layer 20 is first formed on a semiconductor substrate 1. Then, a patterned resist is used to form a trench by anisotropic etching. At this time, the passivation layer 20 remains on the semiconductor substrate 1 on which no trench is formed. A region in which the passivation layer 20 remains includes an active semiconductor region on which a semiconductor device such as a transistor is to be formed. After an oxide film 21 is formed on an internal wall of the trench, the void 25 is partially filled with a water-soluble glass and is subjected to etch-back. Then, a silicon dioxide layer 23 is provided by using a CVD method. In that case, the silicon dioxide layer 23 is provided in such a manner that films to be provided on both sidewalls have inclinations which are equal to each other. The water-soluble glass is removed through an opening which reaches the water-soluble glass and a silicon dioxide layer 24 is provided by the CVD method. Thus, an isolation trench having the void 25 is formed in the semiconductor substrate 1. The silicon dioxide layers 23 and 24 are polished and flattened by CMP (Chemical Mechanical Polishing). The passivation layer 20 is removed by etching. Thereafter, a transistor or the like is formed in an active semiconductor region 26 as shown in FIG. 39. This method has a problem in that a complicated step of removing the water-soluble glass by using two kinds of CVD methods should be performed if the isolation trench is to be changed into a void. According to a trench structure shown in FIGS. 38 and 39, a surface of the semiconductor substrate 1 and the silicon oxide film 21 intersect each other at an almost right angle. For this reason, an electric field concentrates. If the electric field concentrates in a trench edge, the following phenomena are observed. More specifically, a hump is generated in a gate voltage-drain current characteristic of the transistor, and a reverse narrow channel effect becomes remarkable, that is, a threshold voltage is dropped if a gate width of the transistor is reduced.
The wiring capacitance listed in the item 2 is one of important factors which determine an operating speed of a semiconductor integrated circuit having a large number of transistors. In general, metal is often used for the wire 12 shown in FIG. 37, and oxide is often used for an interlayer film provided between the wires or between the wire and the semiconductor substrate. For example, in the case where a silicon oxide film is used between the wires, a wiring capacitance Cw per unit area is calculated by Equation 3, wherein a wiring distance is represented by t0x and other reference numerals have the same definition as those in the Equation 2. The silicon oxide film has a great dielectric constant, for example, of about 3.9. Therefore, operation of the semiconductor integrated circuit is delayed.                               C          W                =                                            ϵ              0                        ·                          K                              SiO                ⁢                                  xe2x80x83                                ⁢                2                                              ⁢                      1                          t                              0                ⁢                X                                                                        (        3        )            
For example, Japanese Patent Application Laid-Open Gazette No. 3-156929 has described a method for manufacturing a semiconductor device having a vacancy on an interlayer film in order to reduce a wiring capacitance. According to the manufacturing method, aluminum is directly formed, by sputtering, on the interlayer film with the vacancy opened. According to such a manufacturing method, it is necessary to form a vacancy having a small diameter on the interlayer film in such a manner that the vacancy is not filled with the aluminum. If a small cavity is formed by the vacancy, the effects of a reduction in the wiring capacitance are decreased. The problem that the effects of the reduction in the wiring capacitance are decreased with the small cavity also applies to the invention described in Japanese Patent Application Laid-Open Gazette No. 5-283542. Japanese Patent Application Laid-Open Gazette No. 63-318752 has disclosed the invention in which a vacancy is provided between adjacent wirings on the same layer to reduce a wiring capacitance. A plasma CVD SiN film, a plasma CVD SiO film, an atmospheric CVD SiO film and an atmospheric CVD PSG film are formed on the condition of poor height difference covering properties. By using such a method, there is a higher possibility that defective insulation might be caused because the wires cannot fully be covered due to the poor height difference covering properties.
The operating speed of the MOS transistor is greatly affected by the gate-to-source capacitance and gate-to-drain capacitance listed in the item 3. These capacities are parasitic capacities, and are preferably small in order to increase the operating speed of the MOS transistor. Referring to FIG. 37, the gate-to-source capacitance and the gate-to-drain capacitance are generated between the gate/drain regions 3c and 3d interposing the sidewall spacer 8 therebetween and the polysilicon gate electrode 5. By analogical application of the Equation 2, it is apparent that these capacities are reduced if a dielectric constant of the sidewall spacer 8 is decreased.
In order to decrease the dielectric constant of the sidewall spacer 8, it is preferable that a void should be provided on the sidewall spacer 8 in the same manner as in the isolation trench, for example. By way of example, Japanese Patent Application Laid-Open Gazette No. 63-211676 has disclosed a method for manufacturing a MOS transistor comprising a sidewall spacer having a cavity portion. However, even if a lightly doped drain (LDD) structure is formed with the cavity portion provided, an impurity concentration of the source/drain region fluctuates with difficulty.
U.S. Pat. No. 5,516,720 has disclosed a method for manufacturing a MOS transistor comprising a sidewall spacer having a void formed therein. However, the void is only a part of the sidewall spacer and is not formed in a portion which is in contact with a semiconductor substrate. A material making the sidewall spacer adheres to the semiconductor substrate. While impurities are implanted into the semiconductor substrate during formation of the LDD structure, damages remain on the sidewall spacer.
The stress applied to a gate electrode by formation of silicide which has been listed in the item 4 reduces a mobility of carriers (electrons or holes) traveling in a channel. Referring to FIG. 37, stress applied to the gate electrode 5 generates stress on an interface between the gate oxide film 4 and the semiconductor substrate 1. Therefore, the above-mentioned phenomenon occurs. In order to reduce resistance values of the signal wires 9a to 9c, the silicide film 6 is formed on the gate electrode 5. In that case, the following steps are performed. Consequently, the stress is applied to the gate electrode 5. More specifically, refractory metal such as tungsten (W) or titanium (Ti) is provided on the polysilicon gate electrode 5, and heat treatment such as RTA (Rapid Thermal Anneal) is performed to cause polysilicon and the refractory metal to chemically react, thereby forming silicide (WSi, TiSi or the like).
For example, Japanese Patent Application Laid-Open Gazette No. 4-151866 has disclosed that a slit or a hole is provided on a wiring layer (guard ring) to relax stress in a corner portion and the like. However, the disclosed slit width ranges from 20 xcexcm to 40 xcexcm. Accordingly, it is hard to form a slit on a wire whose width is less than about 0.1 xcexcm, for example, by using the technique described in the publication.
The isolation trench of the semiconductor integrated circuit according to the prior art has the above-mentioned structure. Because of etching damages and contact of materials having different coefficients of volumetric expansion, infinitesimal defects are generated on an internal wall of the trench during etching and heat treatment.
In the method for manufacturing a semiconductor integrated circuit according to the prior art, in the case where the void is to be provided to reduce the permittivity of the isolation trench, the step of providing the void on the isolation trench is complicated so that manufacture is hard to carry out.
In the semiconductor integrated circuit according to the prior art, furthermore, there has been a problem that the operating speed of the semiconductor integrated circuit is reduced by the interlayer film provided between the wirings or between the wiring and the semiconductor substrate.
The method for manufacturing a semiconductor device according to the prior art has the following problem. More specifically, if impurities are implanted to form the source/drain region after the sidewall spacer is changed into the void, it is hard to form the LDD structure having a sufficient difference between impurity concentrations of the source/drain regions. In addition, if a size of the void is reduced to form the LDD structure having a sufficient difference in the impurity concentration, the sidewall spacer damaged by ion implantation remains in the source/drain region. For this reason, an interface state is generated on an interface between the sidewall spacer and the silicon substrate so that a part of electrons flowing from a source into a drain are captured by the interface state, thereby causing scattering of a drain current flowing in the vicinity of the interface. Consequently, a magnitude of the drain current is reduced.
In the semiconductor device and the method for manufacturing the semiconductor device according to the prior art, stress is applied to the gate electrode so that the mobility of the carriers in the semiconductor substrate provided under a gate insulation film is decreased. Consequently, current driving force of the transistor is reduced.
A first aspect of the present invention is directed to a semiconductor integrated circuit comprising a semiconductor substrate having a predetermined principal plane, a plurality of elements provided on the predetermined principal plane, and an isolation trench provided on the predetermined principal plane for isolating the elements, wherein the isolation trench is filled with fluoride.
A second aspect of the present invention is directed to the semiconductor integrated circuit according to the first aspect of the present invention, wherein the fluoride is SiOF.
A third aspect of the present invention is directed to the semiconductor integrated circuit according to the first or second aspect of the present invention, further comprising an oxide film formed on an internal wall of the isolation trench by oxidizing the semiconductor substrate.
A fourth aspect of the present invention is directed to a method for manufacturing a semiconductor integrated circuit, comprising the steps of forming an insulation film on a principal plane of a semiconductor substrate on which a plurality of elements are provided, forming a reflow glass on the insulation film, forming, on the principal plane, an isolation trench having a bottom face inside the semiconductor substrate through the reflow glass and the insulation film to isolate the elements, and blocking the isolation trench above the bottom face by causing the reflow glass to be subjected to reflow.
A fifth aspect of the present invention is directed to the method for manufacturing a semiconductor integrated circuit according to the fourth aspect of the present invention, wherein the reflow glass is a boron phosphosilicate glass.
A sixth aspect of the present invention is directed to a semiconductor integrated circuit comprising a semiconductor substrate having a predetermined principal plane, a first wire provided above the semiconductor substrate, a second wire provided between the semiconductor substrate and the first wire, and a supporter isolated from the second wire for supporting the first wire on the semiconductor substrate, wherein the first wire and the second wire are insulated from each other by only a predetermined gas with which a layer space formed between the first wire and the second wire at a predetermined distance from the predetermined principal plane is filled.
A seventh aspect of the present invention is directed to the semiconductor integrated circuit according to the sixth aspect of the present invention, wherein the first wire includes a plurality of bit lines, and the second wiring includes a plurality of word lines.
An eighth aspect of the present invention is directed to a method for manufacturing a semiconductor integrated circuit, comprising the steps of forming an interlayer film on a first wiring layer, forming a reflow glass film on the interlayer film, forming a plurality of trenches perpendicularly to the interlayer film and the reflow glass film, forming a cavity on the trenches by causing the reflow glass film to be subjected to reflow, flattening the reflow glass film after the reflow, and forming a second wiring layer on the reflow glass film after the flattening.
A ninth aspect of the present invention is directed to a method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode on a predetermined principal plane of a semiconductor substrate, forming a first sidewall spacer to cover the gate electrode, forming a second sidewall spacer to cover the first sidewall spacer and to come in contact with the semiconductor substrate, implanting an impurity into the semiconductor substrate by using the gate electrode and the first sidewall spacer as masks to form a source and a drain, and removing the first sidewall spacer.
A tenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the ninth aspect of the present invention, wherein the step of forming a source and a drain is performed by using both the first and second sidewall spacers as masks.
An eleventh aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the ninth aspect of the present invention, the step of forming a source and a drain is performed by using only the first sidewall spacer as a mask.
A twelfth aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate having a predetermined principal plane, stacked layers provided on the predetermined principal plane and including a gate electrode, and a dome-shaped sidewall spacer covering the stacked layers, wherein the sidewall spacer is isolated from the stacked layers by a cavity.
A thirteenth aspect of the present invention is directed to a method for manufacturing a semiconductor device, comprising the steps of preparing a semiconductor substrate having, a predetermined principal plane, forming a gate insulation film on the predetermined principal plane, forming a polysilicon film on the gate insulation film, forming a metal film having a void on the polysilicon film, and siliciding the polysilicon film and the metal film by reaction.
A fourteenth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the thirteenth aspect of the present invention, further comprising a step of forming a sidewall spacer which is higher than the metal film on sidewalls of the gate insulation film, the polysilicon film and the metal film provided on the predetermined principal plane of the semiconductor substrate, wherein the step of forming the metal film includes a step of providing the metal film in a concave portion enclosed by the sidewall spacer and the polysilicon film.
A fifteenth aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate having a predetermined principal plane, a gate insulation film provided on the predetermined principal plane, a polysilicon film provided on the gate insulation film, and a silicide film provided on the polysilicon film, wherein the silicide film has a void.
According to the first aspect of the present invention, dangling bonds can be decreased by the SiOF with which the isolation trench is filled, and a leak current flowing between the elements isolated by the isolation trench can be reduced.
According to the second aspect of the present invention, a dielectric constant of the SiOF is smaller than that of silicon dioxide. Therefore, isolation characteristics of the isolation trench can be enhanced.
According to the third aspect of the present invention, the isolation trench can be protected by the oxide film. In addition, the dangling bonds generated between the oxide film and the semiconductor substrate can be decreased to reduce the leak current between the elements.
According to the fourth aspect of the present invention, the void can simply be formed between the reflow glass and the bottom face of the trench in such a manner that the reflow glass does not enter the bottom face of the trench during the reflow of the reflow glass.
According to the fifth aspect of the present invention, the boron phosphosilicate glass easily causes overhang. Therefore, manufacturing conditions can be relaxed.
According to the sixth aspect of the present invention, a capacity between the first and second wirings can be reduced by the layer space filled with the predetermined gas. Thus, an operating speed of the semiconductor integrated circuit can be enhanced.
According to the seventh aspect of the present invention, a plurality of bit lines and a plurality of word lines are provided so that their superposition is increased. Consequently, the operating speed can be enhanced still more.
According to the eighth aspect of the present invention, the trench can easily be changed into the void by the reflow of the reflow glass.
According to the ninth aspect of the present invention, the first sidewall spacer damaged by the implantation of the impurity is removed. Therefore, it is possible to prevent characteristics of the semiconductor device from being deteriorated by the damage of the first sidewall spacer.
According to the tenth aspect of the present invention, impurity diffusion can be prevented during the formation of the second sidewall spacer, and a size of the device can easily be reduced.
According to the eleventh aspect of the present invention, the second sidewall spacer is not damaged during the implantation of the impurity. Consequently, the characteristics of the semiconductor device can be prevented from being deteriorated.
According to the twelfth aspect of the present invention, the sidewall spacer isolated from the stacked layers by the void transmits stress from the outside to neither the stacked layers nor the gate electrode. Therefore, the leak current can be reduced when the semiconductor device is off.
According to the thirteenth aspect of the present invention, less impurities can be taken into the suicide when the polysilicon is silicided, and a variation in a threshold voltage of a transistor can be reduced.
According to the fourteenth aspect of the present invention, the metal film can easily be formed in the void.
According to the fifteenth aspect of the present invention, the void is formed on the silicide layer. Therefore, stress applied to the gate electrode can be relaxed, and defects and an interface state generated by the stress can be reduced. Consequently, the leak current can be reduced when the semiconductor device is off.
In order to solve the above-mentioned problems, it is an object of the present invention to reduce a leak current caused by infinitesimal defects which are generated due to etching damages on an internal wall and contact of materials having different coefficients of volumetric expansion in an isolation trench of a semiconductor integrated circuit.
It is another object of the present invention to simplify a step of providing a void in an isolation trench to easily manufacture a semiconductor integrated circuit.
It is yet another object of the present invention to enhance an operating speed of a semiconductor integrated circuit by changing, into a void, an interlayer film provided between wirings or between the wiring and a semiconductor substrate.
It is a further object of the present invention to eliminate the cause of scattering of a drain current flowing in the vicinity of an interface by removing a sidewall spacer damaged by ion implantation, thereby preventing the drain current from being reduced.
It is a further object of the present invention to relax stress applied to a gate electrode to prevent a mobility of carriers in a semiconductor substrate provided under a gate insulation film from being reduced and to prevent current driving force of a transistor from being reduced.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.